1. Field of the Invention
The present invention relates to a mounted structure of a laminated capacitor, and a method of mounting a laminated capacitor.
2. Description of the Related Art
On a wiring board having an integrated circuit (IC) mounted thereon, a decoupling capacitor is sometimes mounted between a power supply of the integrated circuit and a ground for the purpose of suppressing voltage variation or removing noise during operation of the integrated circuit. In the case where a decoupling capacitor is mounted, it is desirable that power supply impedance be low in order to suppress voltage variation.
In recent years, with a decrease in voltage and an increase in current of a power supply supplied to an integrated circuit, the need for a target impedance required for a power supply impedance has become increasingly strict. Conventionally, in order to keep the power supply impedance within the target impedance, multiple two-terminal capacitors have been mounted to reduce ESL (Equivalent Series Inductance).
In order to mount multiple two-terminal capacitors on a wiring board, however, the wiring board needs to have a large mounting area. As a method of reducing a mounting area, for example, Japanese Patent Laying-Open No. 2007-329282 discloses a multilayer wiring board including a first signal electrode layer, a ground electrode layer, a power supply electrode, and a second signal electrode layer laminated therein, in which an IC is mounted on an upper surface of the board, while a three-terminal capacitor is mounted on a lower surface of the board. Such use of a three-terminal capacitor having lower ESL than that of a two-terminal capacitor enables a reduction in the number of decoupling capacitors.
In a wiring board having a decoupling capacitor mounted thereon, anti-resonance occurs between the capacity of an integrated circuit and the inductance of the capacitor. As a result of this anti-resonance, power supply impedance increases as the frequency increases on the lower frequency side, and decreases as the frequency increases on the higher frequency side, with an anti-resonance frequency being defined as a boundary. That is, the power supply impedance has a characteristic that is peaked near the anti-resonance frequency. Since there is a possibility that the power supply impedance at this anti-resonance frequency may exceed a target impedance, it is desirable to suppress the anti-resonance.
Examples of methods of suppressing the anti-resonance include increasing the ESR (Equivalent Series Resistance) of the decoupling capacitor. For example, Japanese Patent Laying-Open No. 2009-60114 discloses a laminated chip capacitor including a capacitor body including first and second capacitor units arranged in a direction of lamination, and a plurality of external electrodes provided on a side surface of the capacitor body, in which the first and second capacitor units are provided such that the first capacitor unit has a lower ESL than that of the second capacitor unit and the first capacitor unit has a higher ESR than that of the second capacitor unit. Japanese Patent Laying-Open No. 2009-60114 further discloses that the first and second capacitor units are coupled to each other through a coupling conductor line during mounting of the laminated chip capacitor having this configuration on a circuit board, and that the ESR of the second capacitor unit is substantially increased by serial addition of the resistance of this coupling conductor line to the second capacitor unit. This substantially reduces the difference in ESR between the first and second capacitor units, to produce a constant impedance characteristic over a wide frequency band.
Target impedance may be defined in two stages of a first target impedance in a frequency band smaller than or equal to a boundary frequency, and a second target impedance greater than the first target impedance and in a frequency band greater than the boundary frequency. In order to satisfy this target impedance, a power supply impedance that increases at an anti-resonance frequency needs to be smaller than or equal to the second target impedance, and the power supply impedance needs to be smaller than or equal to the first target impedance at a boundary frequency.
The use of a capacitor having a high ESR as in the method disclosed in Japanese Patent Laying-Open No. 2009-60114 can keep the power supply impedance at the anti-resonance frequency at relatively low level, but increases the power supply impedance on the lower frequency side of the anti-resonance frequency. As such, there is a possibility that the power supply impedance that increases on this lower frequency side may exceed the first target impedance at the boundary frequency. In order to reduce the power supply impedance at the boundary frequency, the ESL needs to be reduced.
Accordingly, in order for the power supply impedance at the anti-resonance frequency to be smaller than or equal to the second target impedance and for the power supply impedance at the boundary frequency to be smaller than or equal to the first target impedance, the ESR and the ESL need to be adjusted to appropriate values to increase the ESR and reduce the ESL. In the method disclosed in Japanese Patent Laying-Open No. 2009-60114, however, since a single capacitor is configured to include the first capacitor unit having a high ESR and the second capacitor unit having a low ESL, accurate adjustment of the ESR and the ESL that can be made with the use of a plurality of capacitors may not be possible. Thus, there is a possibility that the target impedance may be exceeded at either the anti-resonance frequency or the boundary frequency. On the other hand, increasing the number of laminated capacitors for accurate adjustment of the ESR and the ESL will increase a mounting area of the laminated capacitors.